Appendix A, which is part of the present disclosure, is a microfiche appendix consisting of three sheets of micro fiche with a total of 105 frames. Microfiche Appendix A is a listing of a computer program which is described more completely below.
1. Field of the Invention
This invention relates generally to a digital computer subsystem for storing data, and more specifically, to a dynamic random access memory unit which functions as a hard disk storage unit without the latency limitations of a normal hard disk.
2. Description of the Prior Art
All computers regardless of size are comprised of the same basic subsystems, a central processing unit, a means for displaying information, a means for entering information, and a means for storing data. Several means for storing data currently exist including floppy disk drives, tape drives, and hard or fixed disk drives. Floppy disk drives have a limited storage capacity usually one megabyte or less. Tape drives are useful for archiving and backing up data, but tape drives are not appropriate for random access applications. The device most commonly used for storage of large amounts of data is the hard disk drive. The total memory capacity of a hard disk drive can range from 5-1000 megabytes.
The hard disk drive has a rotating magnetic media, a disk, that can be magnetized in a certain pattern and a read/write head which flys above the surface of the disk. During a write operation, the head creates data patterns on the magnetic coating of the rotating disk which represent the data, while in read mode the head reads these data patterns. In most high capacity hard disk drives, several disks are mounted above one another on a common spindle. Each of the disks has at least one head/write head per surface, and commonly several read/write heads may be utilized on each surface. Data is stored intracks which are concentric circles on the disk surface. When a plurality of disks are used on a common spindle, the tracks on the disks are written at the same relative radial position on each disk, that is track one on one disk is directly above (or below) track one on the adjacent disk. The track locations may also be looked as cylinder locations since the location of track one on the stack of disks forms what is referred to as a cylinder which extends perpendicularly to the disk surfaces.
The data stored on the hard disk is generally divided into files. Each file represents a unit of data which is processed by the digital computer. The files are stored on the rotating disk in sectors. The number of sectors which are written in one revolution of the rotating disk comprise a track. While the number of sectors per track is a function of the disk drive and the disk controller, thirty-two sectors per track are common. Since a magnetic servo can position the read/write heads over the entire surface of the disk, the disk surface contains a multiplicity of concentric data tracks. A typical disk has a track density of 1000 concentric tracks over a one inch radius.
The central processing unit, the central processor, of a digital computer must be able to read and write data on the hard disk upon command. The data must be written on the disk so that it can be found when the central processor wants to the read the same data. Controlling a disk drive is a very involved operation and if the central processor were totally involved in disk drive control, the central processor would not have adequate time for other operations such as mathematical computations or data processing. Therefore, the central processor interfaces with the hard disk drive through a disk controller. The central processor issues a request for a file to the disk controller and then goes on to other tasks. The disk controller issues commands to the disk drive, locates the sectors comprising the file on the disk, retrieves the file, and cues the central processor that the file is ready for use.
The disk controller acting as an interface between the central processor and the hard disk drive introduces another problem. Each computer has its own protocol, that is, each computer has a unique bus structure for interfacing the central processor with peripheral devices such as a hard disk drive. To interface a hard disk drive with each of the various buses for the central processing units of different computers would be a very cumbersome task. Accordingly, standard disk protocols have been developed for hard disk drives. Thus, each central processor has its own convention for communication, but the disk controller translates this convention into a standard disk protocol.
Control Data Corporation originated one of the most widely used disk interface specifications, the Storage Module Device (SMD) interface. The SMD interface uses bit serial digital data transfer, a parallel control bus, differential signals, and incorporates error recovery facilities. The SMD interface is widely applied and virtually all the major disk manufacturers build products that comply with the SMD interface. Therefore, means are available for interfacing a hard disk drive with the central processing unit of the digital computer, but hard disk drives are still plagued with two very serious problems, seek time and latency.
Access time is defined as the time span between when the central processor requests information and that information is made available by the disk controller. The major factor in the access time is the large amount of time, the seek time, required to position a head over the desired track of the hard disk. A seek time of 100 milliseconds is not uncommon for hard disk drives. The magnetic servo can only position the head near the desired track. Each sector in a track contains information about the head position, the track, and the sector number within the track. The controller reads this information and through successive approximation between the current position of the read head and the desired position of the read head, the desired track is found.
The 100 millisecond delay time is a significant delay for modern high speed computers, but several factors can make the delay time even greater. After the track requested by the central processor is located, another delay, rotational latency, may be imposed. A typical hard disk makes one complete revolution every 16 milliseconds. If the head is positioned on a track just as the desired sector has gone past, the controller must wait another 16 milliseconds before the desired sector can be read.
A large file may include hundreds of sectors each filled with data. The disk controller can handle only several sectors at a time. Thus, the access time delay is imposed over and over again. Also if a large file is being used simultaneously by many different users of the digital computer, the disk controller is flooded with requests for sectors located throughout the disk.
While these problems are widely recognized, the high speed rotation of the disk, the ability to precisely position the read/write heads, and the geometry of the disk severely limit the choices in addressing these problems. The options available for improving access time include increasing the rotation speed of the disk, increasing the storage density of the disk, or enhancing the storage efficiency on the disk.
To better understand the limitations of the current hard disk drives, consider the information written in each sector on the hard disk by the SMD disk controller. As shown in FIG. 1a, each sector 10 is comprised of several fields in addition to the data field. The first information at the beginning of each sector is the head scatter field 11. This field 11, typically sixteen bytes long, is provided to compensate for the inability of a normal hard disk drive to go instantaneously from reading to writing. Immediately after the head scatter field 11 is the PLO sync field 12 which is typically ten bytes in length. The PLO sync 12 is a sync signal that permits the controller to compensate for variations in the disk speed from disk to disk or from time to time. Next is the address field 13 of the sector 10 which comprises eight bytes and is further broken down as shown in FIG. 1b. 
The address field 13 is a unique field for each sector on the disk. It provides information on the sync pattern 13a, flag status and logical unit 13b, the upper cylinder 13c, lower cylinder 13d and the head and sector 13e plus two cyclic redundancy checking (CRC) code bytes 13f, 13g. Following the address field 13 is a write splice field 14 which is typically one byte. This is followed by another PLO sync field 15 of ten bytes and a sync pattern field 16 of one byte.
After fields 11-16 is the data field 17 in which the central processing unit may store data on the disk or read data from the disk. The data field 17 is followed by a two byte CRC field 18 and then the one byte end of record pad field 19, followed by an eight byte end of sector field 20.
On a typical hard disk, only 81% of the storage capacity is actually used for data storage. The remaining storage capacity is used to store the additional fields for each sector as shown in FIG. 1. Typically, only the 8 byte address field and the data field are unique to the sector. The data in the other fields is similar for each of the sectors in a track.
In locating a desired sector, the disk controller issues a seek command. A conventional hard disk drive then issues a pair of signals, a sector pulse and an index pulse. The sector pulse is issued to the controller at the beginning of each sector and the index pulse is issued once per revolution of the disk. The SMD disk controller issues a read gate signal immediately after receiving the sector pulse. The hard disk drive upon receipt of the seek command positions the read/write heads. Upon receipt of the read gate signal, the disk drive reads the head scatter, PLO sync, and the address fields of the sector over which the read head is currently positioned and sends the information to the SMD disk controller. The SMD disk controller always deasserts the read gate at the write splice field of the sector. Next, the controller initiates one of three actions;
1. If this is the sector to read, read gate is reasserted.
2. If this is the sector to write, write gate is asserted.
3. If this is not the sector of interest, neither gate is asserted.
If it is not the correct track, the head moves to a new location based upon the current position and the position requested by the central processor and reads again. This process continues until the correct track is found. A read gate or write gate signal is asserted by the disk controller when the desired sector and track are found.
To overcome the problems associated with hard disk drives requires eliminating or substantially reducing the access time of the disk drive as well as providing better means for storage of data. The prior art has considered increasing the rotational speed of the hard disk, increasing the storage density of the hard disk, and increasing the efficiency of data storage on the hard disk as means for improving the performance of a hard disk drive. Another solution would be to replace the hard disk with solid state memory. Solid state memory has the advantages of a very fast access time and very good reliability because it is not an electromechanical device, but the SMD interface was conceived to control disks and rotating medium and not to control any type of solid state memory. Therefore to replace the hard disk with solid state memory requires that the solid state memory appear as a disk to the SMD disk controller. This invention overcomes the problems of the prior art by providing a means for directly interfacing a solid state memory with a SMD disk controller.
The disk emulator of this invention is a solid state system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time.
In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. While different circuits are required to generate the signals necessary for the write operation and for the read operation, the use of the shift register, parity circuit and latch circuit in conjunction with the 66-bit parallel bus and the DRAM array for both the read and write operations minimizes the circuitry in the disk emulator. Consequently, both the cost and the size of the disk emulator are reduced.
The 66-bit shift register receives serial data from the SMD disk controller and converts the stream of serial data into 66-bit words which are each passed over the 66-bit parallel bus to the latch circuit where they are temporarily stored. For each 66-bit word a parity bit is also generated by the parity circuit. The stored word in the latch circuit and the associated parity bit are transferred to the DRAM array over the 67 bit (that is 66 bits of data+1 parity bit) parallel bus while another word is being serially supplied to the 66-bit shift register by the SMD disk controller.
In this embodiment, each track of data in the disk emulator may be comprised of thirty-two sectors, with each sector being comprised of sixty-four 66-bit words. This word length allows the memory interface timing to be very conservative while still maintaining a very fast transfer rate to the SMD disk controller. An additional benefit of the 66-bit word is the economy of parity. For a long word, the stored parity bit is a small portion of the stored data.
To further reduce the memory requirements for the DRAM array of the disk emulator, only the sector-specific data provided by the SMD disk controller are stored in the DRAM array. In each sector on a disk, only the address field and the data field are unique. Accordingly, the disk emulator needs to store only address information and the data information and does so by making the zeroth word of the sector in the DRAM array the address field and the first through sixty-third words of the sector in DRAM array the data field. Since only the sector-specific data, the address field and the data field, are stored in the DRAM array, approximately 97% of the DRAM array is used for data storage while in a typical hard disk only 81% of the disk is available for data storage. Hence, the ability of the disk emulator to store only sector-specific data significantly enhances the utilization of the storage medium over prior art systems.
Another unique feature of the disk emulator concerns data integrity. Solid state memory errors can be divided into two basic types, hard errors and soft errors. The SMD disk controller corrects soft errors which are random, single bit errors in the data retrieved from the DRAM array. However, hard errors are the result of a catastrophic memory failure in the DRAM array and generally affect many bits within the array. Hard errors require an error correction process to correct the stored data before the data are supplied to the SMD disk controller. Prior art error correction process typically used an 8-bit ECC code and a mathematical process which operated on the ECC code to correct hard errors. However, an 8-bit per word overhead would add significant cost to a disk emulator. Accordingly, a novel error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.
In the error correction process, as each word is retrieved from the DRAM array of the disk emulator, a new parity bit is generated for the stored word. The new parity bit is compared with the stored parity bit for the stored word. If the two parity bits are the same, no error has occurred and the normal read cycle for the disk emulator is followed. However, if the two parity bits are different, an error has occurred and the disk emulator uses the novel error correction process to correct the word.
In the error correction process, the retrieved word is inverted and latched in the latch circuit of the disk emulator. The inverted word is then written to the same location in the DRAM array from which the original word was retrieved. The inverted word is then again retrieved from the DRAM array, inverted and latched in the latch circuit. Then, at the appropriate time, the error corrected word is passed from the latch circuit over the 66-bit parallel bus to the 66-bit shift register from which the error corrected word is serially supplied to the SMD disk controller.
This novel READ/INVERT/WRITE/READ/INVERT/WRITE error correction process, using only a parity bit, corrects a single bit hard memory error while the previous word is being serially supplied to the SMD disk controller. With the design of the latch circuit, i.e., the use of inverting latches, and this novel six step error correction process, the error correction process is completed in a time frame such that the disk emulator can operate at data rates as high as 50 Megahertz. Thus, the new error correction process not only conserves storage space in the DRAM over prior art processes, but also corrects errors with such speed that the disk emulator operates at the highest frequency permitted by the SMD interface convention.
When the SMD disk controller wants to read data from the disk emulator or write data to the disk emulator, the SMD controller sends a seek command to the disk emulator. The SMD disk controller simultaneously provides the cylinder and head address for the desired data over the SMD control cable. The combination of the cylinder and head address defines a unique track since each head can access predetermined cylinders on one disk surface. Differential current mode receivers in the disk emulator translate the differential signals from the SMD disk controller to logic signals.
The ROM translation circuit in the disk emulator instantaneously translates the geometric addresses from the SMD disk controller, the cylinder and head address, into higher order addresses for the DRAM array in the disk emulator. In the disk emulator, higher order addresses refer to the addresses for the DRAM array which correspond to the cylinder and head address from the SMD controller. Lower order addresses are also used in the DRAM array and that term refers to the addresses in the DRAM array which correspond to the sector and the words within a sector.
Since the translation of the geometric address information from the SMD controller to the higher order addresses is virtually instantaneous, the microprocessor in the disk emulator can, upon receiving the seek command, immediately issue an index pulse to the SMD controller indicating that the desired head has been located over the desired cylinder, i.e., indicating that the track containing the designed sector has been located. The microprocessor then enters the rapid sector cycle. In the rapid sector cycle, the microprocessor initially generates the address corresponding to the zeroth sector of the track specified by the SMD disk controller.
The index pulse sent to the SMD disk controller is also used to initialize the disk emulator. The index pulse clears programmable counters, used to generate timing signals, the shift register and other components in the disk emulator. In addition, other programmable counters, used to address the words in a sector, are initialized such that the zeroth word of the sector is addressed.
Since the SMD disk controller provided information which was translated into the higher order address and the disk emulator generated the lower order address for the zeroth word of the zero sector of the track specified by the SMD disk controller, the location in the DRAM array of the word that will initially be provided to the SMD disk controller is completely specified. Accordingly, the disk emulator fetches the zeroth 66-bit word for the zeroth sector (which is the address field for the zeroth sector) in the track specified by the SMD controller plus the one parity bit for the zeroth word and provides the word to the latch circuit and parity circuit on the 66-bit parallel bus.
At this time, the parallel terminals of the shift register, which are also connected to the 66-bit parallel bus, are tri-stated to prevent contentions on the 66-bit parallel bus between data in the shift register and the zeroth word being retrieved from the DRAM array. Thus, the zeroth word from the DRAM array on the 66-bit parallel bus is available only to the parity circuit and to the latch circuit. The parity circuit generates a new parity bit for the zeroth word on the 66-bit parallel bus and the error correction circuit compares the stored parity bit with the new parity bit and as described previously, the stored word is error corrected if the two parity bits are different.
Hence, after the seek command from the SMD disk controller and the index signal from the disk emulator, the zeroth word, the address field, for the-zeroth sector of the track specified by the SMD disk controller is loaded in the latch circuit and is ready to be loaded into the shift register and serially transmitted to the SMD disk controller.
Immediately after the SMD disk controller receives the index pulse from the disk emulator, the SMD disk controller asserts the read gate signal to the disk emulator. At this time, the disk emulator starts to supply a series of zero bits to the SMD disk controller which correspond to the first gap in the sector, i.e., the region from the start of the sector to the address field of the sector.
The disk emulator counts the number of bytes supplied to the SMD controller and precisely when the number of bytes in the sector prior to the address field is reached, the disk emulator loads the address field from the latch circuit over the parallel bus into the shift register which subsequently serially shifts the address field to the SMD controller. While the address field is being serially supplied to the SMD controller, the disk emulator retrieves the first word of the zeroth sector from the DRAM array, error corrects the word, and stores the word in the latch circuit.
After the SMD disk controller receives the address field, the controller deasserts the read gate at the write splice field of the sector and initiates one of three actions: (1) if this is a sector to be read, the SMD disk controller reasserts the read gate; (2) if this is a sector to be written the SMD controller asserts the write gate; or (3) if this is not the sector of interest, neither the read gate nor the write gate is asserted by the SMD disk controller.
Accordingly, the microprocessor of the disk emulator polls the read gate signal and the write gate signal from the SMD disk controller for a predetermined time after issuing the address field (in this case for the zeroth sector) and if neither the read gate nor the write gate signal is reasserted, this indicates that this is not the sector which the SMD controller desires and a sector pulse is generated by the microprocessor and transmitted to the SMD disk controller. The microprocessor also increments the address of the DRAM array to the first sector in the track specified by the SMD disk controller.
The sector pulse initializes the disk emulator in a manner that is identical to that previously described for the index pulse. Hence, the zeroth word, the address field, for the first sector of the track specified by the SMD disk controller is retrieved, error corrected, and stored in the latch circuit.
In response to the sector pulse, the SMD disk controller asserts the read gate and the disk emulator again provides the zero bits for the first gap prior to the address field and after the first gap is finished the zeroth word, the address field, of the first sector of the track requested by the SMD disk controller is loaded into the shift register and serially provided to the SMD disk controller. While the address field for the first sector is being provided to the SMD disk controller, the disk emulator retrieves, error corrects and stores the first word of the data field of the first sector in the latch circuit.
The read gate signal and the write gate signal from the SMD disk controller are again polled for the predetermined time after the initiation of the sector pulse and address field and if neither the read gate nor the write gate is reasserted, another sector pulse is generated by the microprocessor and the zeroth word for the second sector is provided to the SMD disk controller in the same matter as described for the zeroth sector and the first sector. The microprocessor continues in this rapid sector cycle mode to initiate a series of read cycles on the zeroth word of consecutive sectors in the track until the read gate or the write gate is asserted by the SMD disk controller.
Thus, the address fields are read by the SMD disk controller at rapid intervals, typically about 10 microseconds, until the desired sector is found. If the desired sector is the last one on the tract, i.e., the thirty-second sector, 320 microseconds are required to locate the sector. A conventional hard disk drive can require sixteen milliseconds to locate the correct sector after the track is located. Hence, the disk emulator of this invention reduces the average rotational latency by a factor of 500. This represents a significant increase in the performance over a conventional hard disk drive and the rotational latency of the disk emulator is no longer the limiting factor in the response of the disk system. Now, the performance of the SMD disk controller and the disk emulator is bounded by the response time of the SMD disk controller. Accordingly, to further improve the rotational latency requires a change in the SMD interface convention.
When the address field provided to the SMD controller corresponds to the sector sought by the SMD controller, the SMD controller reasserts the read gate if the central processing unit driving the SMD disk controller has requested the data stored in that sector. When the read gate is reasserted, the microprocessor leaves the rapid sector cycle and the disk emulator provides a string of zeros, corresponding to the second gap in the sector which is the space between the address field (field 13) and the first word in the data field, to the SMD disk controller.
At the precise time the number of bytes in the second gap is completed, the error corrected first word of the data field is loaded into the shift register and serially supplied to the SMD disk controller. While the first word of the data field is being supplied to the SMD disk controller, the second word of the data field is retrieved from the DRAM array, error corrected and stored in the latch circuit, and when the last bit of the first word leaves the shift register the second word is loaded into the shift register and serially provided to the SMD disk controller. This process continues until the sixty-third word of the sector, which is the sixty-fourth and final word of the sector because the first word was the zeroth word, is provided to the SMD disk controller. After the sixty-third word leaves the shift register, the disk emulator is disabled and provides a series of zero bits to the SMD controller until another sector or index pulse is generated.
When the central processor, which drives the SMD controller, wants to write data to the disk emulator, the initial sequence of actions is identical to those in the read operation. The SMD disk controller issues a seek command and provides the cylinder address and head address to initiate a write to the disk emulator. The microprocessor upon receipt of the seek command and cylinder and head address immediately issues an index pulse and enters the rapid sector cycle. The initialization of the disk emulator and the retrieval of the zeroth word for the zero sector of the track requested by the SMD disk controller are identical to that previously described. Accordingly, the SMD controller again reads the zeroth word and deasserts the read gate at the write splice portion of the sector. Next the controller initiates one of two actions; (1) if this is the sector to write, the write gate is asserted; or (2) if this is not the sector of interest, the write gate is not asserted.
If the write gate is not asserted, the microprocessor continues to rapidly supply the zeroth word for the next sector (sector one) in the track and then polls the write gate and the read gate to determine whether either gate is asserted as previously described. When the correct sector is located and the write gate is asserted by the SMD disk controller, serial data is clocked into the shift register and the microprocessor leaves the rapid sector cycle mode.
A comparator circuit in the disk emulator, which is programmed to detect the data sync pattern prior to the address field, monitors the data in the shift register. When the data sync pattern is detected, after two additional clock pulses to the shift register, a signal is generated which captures the first 66-bit word of the data field which includes the data sync pattern in the latch circuit. The locations in the shift register, which are monitored by the comparator circuit, are selected such that when the data sync pattern is detected, two additional clock pulses to the shift register are required to load the first full 66-bit word of the data field completely into the shift register. While the next word is entering the shift register the 66-bit word stored in the latch circuit and the associated parity bit are written to the DRAM array over the 67-bit parallel bus which consists of the 66-bit data bus and the parity bit line, respectively. Also, the address for the DRAM array is incremented to the next data word of the sector.
This sequence of operations is repeated for the second data word through the sixty-third data word of the sector. Thus, sixty-four words are written to the DRAM array for each sector. In addition to the 66 bits of data information, a parity bit is generated by the circuitry in the disk emulator and is stored in the DRAM array as a 67th bit. After the sixty-fourth word is written to the DRAM array, the disk emulator is disabled until the SMD disk controller issues another sector or index pulse.
Since the DRAM array of the disk emulator is a volatile memory storage element, the disk emulator contains back-up systems which protect the integrity of the data in the DRAM array in the event that the power supply voltage is disrupted.
The disk emulator of this invention significantly improves both the seek time and the sector rotational latency. Also, the data storage medium in the disk emulator is used more efficiently than the data storage medium in a conventional hard disk. Finally, since the disk emulator has no mechanical or moving parts and since the novel error correction process corrects hard memory failures, the reliability of the disk emulator should be significantly better than the reliability of prior art hard disk drives.